 |
| Functional verification |
| Power-aware functional verification & modeling |
| Transaction-based verification, modeling & acceleration |
| Hardware/software co-verification - ISX |
| Verification planning and management |
| Testbench development and automation |
| Assertion-based Verification |
| Formal Analysis |
| Simulation debug and analysis |
| Analog-mixed signal system verification |
| Silicon debug in-circuit emulation |
| Platform VIP Reuse |
|
| Digital IC design |
| RTL synthesis |
| Formal verification |
| Low-power design/estimation in front end |
| Low power design implementation and analysis |
| Design for test/yield/manufacturing (DFT, DFY & DFM) |
| Constraints management and timing analysis |
| Hierarchical layout, prototyping, and planning |
| Physical optimization, routing and timing closure |
| Dealing with ECOs |
| Coping with variation during implementation |
| Signoff (timing, power and SI) |
| Physical verification (DRC, LVS, EM) |
| New technologies challenges |
| IP design and reuse |
| High-performance design |
|
| Custom IC design |
| Analog/RF parasitic extraction and simulation |
| High-frequency challenges and solutions |
| Statistical simulation |
| Circuit optimization |
| Full custom floorplanning |
| Physical automation/ optimization |
| Physical verification |
| Voltage drop/electromigration |
| Mixed-model/mixed-signal simulation and analysis |
| Test for analog/mixed-signal designs |
| IC 6.x Adoption |
| Deep submicron challenges/solutions |
| Modeling/characterization |
| Analog/Mixed signal methodology enhancement |
| RF Design methodology enhancement |
|
| Silicon-Package-Board |
| Front-end design capture |
| Constraint-driven design |
| Design partioning and reuse |
| Library and data management |
| Integration with PLM systems |
| Infrastructure and customization |
| Interactive and automatic routing |
| Design for manufacturing and testability |
| Signal and power integrity analysis |
| Simulation model development |
| Multi-gigahertz design |
| Design process and automation |
| Algorithmic-based model development |
| Designing in DDR2 memories |
| Silicon/Package co-design |
| Rapid feasibility prototyping methodologies |
| DFM verification of complex IC Packages/SiPs |
| Package-On-Package design techniques and challenges |
| RF SiP methodology enhancement |
|
| Special Interest |
| OpenAccess |
| Reliability modeling |
| Design for test/manufacturing and RET signal integrity |
| Design reuse strategies |
| Impact of standards on design optimization |
| Configuration management |
| Process design kit automation |
| Platform-dependent methodology flows |
| Linking of design and fab data to improve ramp yield |
| DFY/DFM optimization techniques and results |
| Interoperability |
發表於 2007-4-29 09:32 PM
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發表於 2007-11-28 09:18 AM
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