[問題求助] 大家好，我是新成員，問一個小問題

kyopc

首先，感謝各位撥冗來看我這帖子
. _; L; @" g+ ?! j這個問題算不上是設計，是一個小小的問題
% I6 t7 v, }0 w- h' }我現在有一個CPU的source code,
7 u2 H+ ]! c; K6 L! s7 E$ ?memory的部份是有一個interface來接收FPGA晶片外部的SRAM資料. |1 I- X5 o: e; P8 Q$ C# V2 f: ]
memory資料寬度32bit的
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要把他download到我的板子上
, v9 T  O# Q6 p) S5 p! W) y+ j但是我的板子上的SRAM只有16bit' h" m) K# Z7 H! H) N- f
請問我要怎麼改寫裡面的VHDL code來符合
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; A8 F" |" j: A5 s: r: D0 g/ m可能對板上的高手來說，這是基本問題& n+ W- T! E1 ?, L1 e# A! X
但是我本身不是VLSI設計背景的人
* K6 f9 ?" M, _9 y( x' N! W老闆硬要我搞出來 >_<
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希望大家不吝給我一點提示,謝謝大家

tommywgt

就算是32BITS CPU也允許16BITS的存取才對, 在這情況下, 什麼都不用修改的, 只需要修改軟體的程式
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如果一定要做到軟體都不用改的話, 影響的範圍比較大, 你可能需要:
: N! s/ u' E5 w! A1) SRAM工作於CPU的兩倍頻率* q3 C0 T: ^0 B: K+ L/ l! j9 d( y
2) 利用類似BE信號 (BYTE ENABLE)來控制SRAM的存取
2 J' ]0 _2 A+ u4 {0 C) y3) 如果SRAM速度跟不上CPU, 而且又不想降頻的話, CPU要能支援類似BUSY的控制信號
5 s) m! z) u8 B# d/ N差不多如此吧, 還有其他我漏掉的嗎???

jason_lin

沒錯,就版主的方式,不然就設計一個FIFO SRAM Controler,丟到fifo裡,讓他自己丟到sram,
! z+ B( S  l4 @4 f1 ?7 \如果完全不會寫hdl,那你去網路上收尋,應該有人寫好的吧!6 S9 U- `% X" S7 o* o) ^7 D
不然Xilinx有提供memory的參考設計,有含HDL code,如下列網址:+ T: U$ O" E& \4 ^+ Z5 v" G
http://www.xilinx.com/products/design_resources/mem_corner/1 J% n: f5 _+ m
你找找,Xilinx的參考設計編號都是XAPP***.pdf,裡面有一個Design file的網址,就是下載soure code的地方^__^
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kyopc

感謝兩位前輩的指導7 [7 w4 s2 d6 `* F$ b8 d. T
由於工作需求，我的程式是沒辦法改的
( q- f( m  i6 b& @換句話說，我必需修改我的硬體
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我會先試試看jason大大的方法，結果再回報給大家1 q/ M# i- ]- F5 m% o
提供經驗給大家2 Z3 s+ Z  I8 Q$ f! S0 q8 b
謝謝

tommywgt

Xilinx的XAPP好多, jason_lin有意願整理歸類一下, 發個文跟大伙介紹一下嗎?6 t# A4 ^  S4 p2 M7 G2 o) s$ @
就以Xilinx的Vertical Segment分類來整理如何? , l) d6 B2 k% [
另外並不是所有的XAPP都有source code的, 可能也要說明一下, 大伙才能更清楚.
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, H7 S6 O9 {( R* p9 w先謝囉!

jason_lin

我整理了一些而已ㄝ,如下:3 f: v$ ]% Z* [3 B; |
FPGA
/ W1 e# x2 o, D0 A. F6 t# aXAPP058        Xilinx In-System Programming Using an Embedded Microcontroller&nbsp;
* ^! R5 s" Q0 D. kXAPP195        Implementing Barrel Shifters Using Multipliers&nbsp;( Z/ Q& @3 k1 p5 a+ I  Y; b
XAPP211        PN Generators Using the SRL Macro&nbsp;& G' B, Y/ {, ~) ^% q" N
XAPP217        Gold Code Generators in Virtex Devices&nbsp;
" c3 g7 ?" e4 u4 p* @+ ?XAPP220        LFSRs as Functional Blocks in Wireless Applications&nbsp;. \* |8 H9 t2 E5 @. R- c% g
XAPP224        Data Recovery&nbsp;
, q! i- P; n' x) @* ]+ nXAPP228        Quad-Port Memories in Virtex Devices &nbsp;. D0 P, B, i( c. V
XAPP229        Wider Block Memories&nbsp;
* D5 r9 P/ m* H) {# X7 a: p. qXAPP250        Clock and Data Recovery With Coded Data Streams&nbsp;
; S: U! s; b0 {- @$ \% I- ~XAPP258        FIFOs Using Virtex-II Block RAM&nbsp;/ F, q4 H8 ~0 `( L- q
XAPP260        Using Virtex-II Block RAM for High Performance Read/Write CAMs&nbsp;
9 Z, `- }; w7 K% uXAPP261        Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory&nbsp;/ e' U0 Q* z% C8 j
XAPP267        Parity Generation and Validation for the Virtex-II Series&nbsp;
9 y% J3 O1 y. ^+ p- T" e* yXAPP268        Active Phase Alignment&nbsp;* ?1 H6 o& c4 d# J
XAPP284        Matrix Math, Graphics, and Video&nbsp;0 n' D& U# I9 n6 g5 ~
XAPP291        Self-Addressing FIFO&nbsp;
& Y0 Y4 i# c9 P4 d/ PXAPP441        Remote FPGA Reconfiguration Using MicroBlaze or PowerPC&nbsp;6 p, M  g- u; j) Y; P
XAPP445        Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories&nbsp;
9 T/ G' ~9 E; L; d. IXAPP454        DDR2 SDRAM Memory Interface for Spartan-3 FPGAs&nbsp;( t# l3 P1 ^' y6 d, {1 w
XAPP462        Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs&nbsp;
4 R$ x+ I6 t. ~. u% XXAPP463        Using Block RAM in Spartan-3 Generation FPGAs&nbsp;1 T/ F2 ~+ U9 d# [; N% }
XAPP464        Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs&nbsp;
2 P% ~; k1 @; L; H; f4 _  {- D! `XAPP465        Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs&nbsp;0 P- a8 W9 K6 Z" T' M
XAPP466        Using Dedicated Multiplexers in Spartan-3 Generation FPGAs&nbsp;
1 s4 |4 X6 E" kXAPP467        Using Embedded Multipliers in Spartan-3 FPGAs&nbsp;$ f$ b: k- h, W0 P$ C+ g3 x5 f! W
XAPP473        Using the ISE Design Tools for Spartan-3 FPGAs&nbsp;0 e( O% l" `7 p+ c% |# O: p  a, F
XAPP474        Using IP Cores in Spartan-3 Generation FPGAs&nbsp;2 `" Z; y% ^" Y' m6 q( {( z; v2 g
XAPP475        Using IBIS Models for Spartan-3 FPGAs&nbsp;2 }+ G6 x  f* O3 x
XAPP476        Using BSDL Files for Spartan-3 Generation FPGAs&nbsp;6 S% Y' r/ t' x, Q# {
XAPP477        Embedded Processing and Control Solutions for Spartan-3 Devices&nbsp;+ ~  x. D2 T3 i5 F" D# c, K* ~
XAPP482        MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage&nbsp;
# A7 D6 O$ b& e* n* J5 MXAPP483        Multiple-Boot with Platform Flash PROMs &nbsp;$ u& v' }8 B& v2 B; m* N7 M
XAPP485        1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps&nbsp;
6 O5 B9 u/ G$ d5 r8 D6 x$ jXAPP489        Four- and Six-Layer, High-Speed PCB Design for the Spartan-3E FT256 BGA Package&nbsp;, \( m: O1 {* W/ C0 H' q
XAPP491        Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs&nbsp;
/ U, _1 |. c8 o* k5 p9 I8 {+ L/ dXAPP500        J Drive: In-System Programming of IEEE Standard 1532 Devices&nbsp;
8 I: C! F2 D5 ?XAPP502        Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode&nbsp;1 l9 C: w3 M6 n3 ?8 p7 z6 k
XAPP514        Audio/Video Connectivity Solutions for the Broadcast Industry
7 n; C+ v/ O8 M3 l# g1 BXAPP529        Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link(FSL)&nbsp;, ~8 r$ x4 v+ f
XAPP535        High Performance Multi-Port Memory Controller
0 l: ]( C/ b% n! zXAPP536        Gigabit System Reference Design (XAPP536)
. P4 i+ {- z6 C7 y% P, `6 dXAPP562        Configurable LocalLink CRC Reference Design&nbsp;3 o% b5 h3 ^" s2 K* D
XAPP569        Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations&nbsp;/ K% q  d( \, {- S& Q  t! X2 L8 y
XAPP622        644-MHz SDR LVDS Transmitter/Receiver&nbsp;
1 E- [" d5 M$ g- {! qXAPP623        Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors&nbsp;
* F! _) d" y$ l$ T$ e$ ]XAPP634        Analog Devices TigerSHARC Link&nbsp;
) p% t! J; a, t+ h* ?XAPP636        Optimal Pipelining of the I/O Ports of the Virtex-II Multiplier&nbsp;5 n# N3 }8 R$ a% v3 ]
XAPP689        Managing Ground Bounce in Large FPGAs&nbsp;
: A. T) H7 {' f7 ZXAPP690        Using Block SelectRAM Memories as Serializers or Deserializers&nbsp;
7 ~5 P" ]3 o3 O$ {, H4 X3 h( SXAPP693        A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs&nbsp;% W& u& S$ H5 S  e; A9 {+ [
XAPP694        Reading User Data from Configuration PROMs&nbsp;: ~  l1 }5 X/ O; B8 Z: m! v
XAPP753        Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF&nbsp;8 B( Z0 S$ o( r1 d: [7 Z1 ~' O; N
XAPP774        Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs&nbsp;6 ^- d7 `% ?- h* Z5 V+ h
XAPP780        FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs&nbsp;; ^, f3 F) t9 `* g8 Z2 A$ W
XAPP806        Determining the Optimal DCM Phase Shift for the DDR Feedback Clock&nbsp;
& t& o- D. N( }8 O% AXAPP909        Reference System: MCH OPB SDRAM with OPB Central DMA&nbsp;
3 I4 |9 {: k/ T5 G. c: Q+ M* wXAPP923        Reference Design: MCH OPB EMC with OPB Central DMA&nbsp;! X$ r, U: I/ |0 q: F1 L
XAPP930        Color-Space Converter: RGB to YCrCb&nbsp;7 K$ ]6 U+ a$ X4 j/ {" j% r
XAPP931        Color-Space Converter: YCrCb to RGB&nbsp;, C# Q/ W: Z" v% w9 j
XAPP932        Chroma Resampler&nbsp;
) s9 }4 M: V7 ^XAPP933        Two-Dimensional Linear Filtering&nbsp;
; \% Y3 x, ~' Y" O2 d7 a8 {5 w% GXAPP936        Continuously Variable Fractional Rate Decimator&nbsp;
( [# K7 Z6 D0 d$ T( p  oXAPP948        Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator&nbsp;
2 d1 w2 y) e8 m# x0 c) g% YXAPP253        Synthesizable 400 Mb/s DDR SDRAM Controller
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tommywgt

能有系統的整理嗎?
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9 g4 `. e% D$ }" X3 k5 H# q造福大家靠你囉...